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	<title>Modelsim - Revision history</title>
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	<updated>2026-04-14T21:55:01Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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		<id>https://makerhub.georgefox.edu/w/index.php?title=Modelsim&amp;diff=11867&amp;oldid=prev</id>
		<title>Gspivey at 00:51, 9 September 2025</title>
		<link rel="alternate" type="text/html" href="https://makerhub.georgefox.edu/w/index.php?title=Modelsim&amp;diff=11867&amp;oldid=prev"/>
		<updated>2025-09-09T00:51:41Z</updated>

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				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;Revision as of 00:51, 9 September 2025&lt;/td&gt;
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		<author><name>Gspivey</name></author>
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		<id>https://makerhub.georgefox.edu/w/index.php?title=Modelsim&amp;diff=7278&amp;oldid=prev</id>
		<title>Gspivey: Created page with &quot;{{#set:  |Is software=True  |Has name={{PAGENAME}}  |Has icon=File:Modelsim_logo.jpg  |Has icondesc=Modelsim Icon  |Has image=File:Mentor_image.jpg  |Has description=HDL Simul...&quot;</title>
		<link rel="alternate" type="text/html" href="https://makerhub.georgefox.edu/w/index.php?title=Modelsim&amp;diff=7278&amp;oldid=prev"/>
		<updated>2020-07-27T20:03:25Z</updated>

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&lt;br /&gt;
In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.&lt;br /&gt;
&lt;br /&gt;
The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF). &lt;br /&gt;
&lt;br /&gt;
== Installation ==&lt;br /&gt;
Click this link to be directed to our internal site for {{PAGENAME}} install instructions and download [https://makerhub-internal.georgefox.edu/wiki/{{PAGENAME}} internal site]&lt;/div&gt;</summary>
		<author><name>Gspivey</name></author>
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